3-level Control Structure
- Unique (ISR/LSR/Task) architecture permits optimum control.
- Deterministic Task Switching
- Deferred Interrupt Processing
Sophisticated Messaging System
- Built upon sending messages to Exchanges.
- Message Prioritization Utility
- Message Safety via use of message control blocks.
- Reduce RAM Usage
- Fine Grained vs. Coarse Grained Task Structure
- Increased Performance due to utilization of on-chip SRAM
- Minimize the harmful effects that long I/O latencies have on control performance.
- Remove endemic problems for real-time control systems such as sampling and latency jitters.
smx® Kernel, of course, also provides the customary task management, memory management, semaphores, mutexes, event management, I/O timing, and miscellaneous special purpose functions.
Breadth of Core Architecture Support
- Ease of migration from evaluation board to custom target.
- Well defined porting layers for supporting new processors.
- Out-of-the-Box Experience
- Decades of evolution in supporting numerous processors with the considerable variety of ways in which interrupts, traps, timers, memory, console, boot, and exit are handled.
- Extensive Middleware Support for Device Peripherals
Board Support Packages
- BSP Start-up Code and Device Drivers
- Tool Support
- BSP Notes
- smxBSP™ API
- Available for Mainstream Evaluation Boards
smx® kernel Brochure